1. Field of the Invention
The invention relates to a multistage process for producing a smooth polycrystalline silicon layer, in particular one with low arsenic doping, for very large scale integrated circuits, by the thermal decomposition of gaseous compounds containing the elements, in which a doped layer and an undoped silicon layer above the doped layer are deposited directly one after the other in a two-stage process.
The production and use of polysilicon layers in the production of VLSI semiconductor circuits is known, for example, from a book entitled "Technologie hochintegrierter Schaltungen" [Technology of Large Scale Integrated Circuits], 1988, by D. Widmann, H. Mader and H. Friedrich (see particularly section 3.8 and FIG. 5.3.2.). In that book, the use of a (doped) polysilicon layer as a second, upper capacitor electrode in the production of a trench memory cell is also described.
In the development of the very large scale integrated components, such as the 4-megabit DRAM (referred to as "4M"), since the planar cells of the capacitor memory cells require so much space, they are increasingly being replaced with trench cells having a high aspect ratio a (wherein a=the ratio between the cell depth and the cell diameter). For the 4M, the trenches are selected with an aspect ratio of greater than or equal to three. Above all, the use of such trench cells leads to a gain in surface area and thus to a larger scale of integration, if the cells are to be disposed as close as possible to one another. In order to ensure that the electrical properties are not impaired by dense packing of the trench cells, it is necessary for the 4M that the n.sup.+ doping (arsenic) of the first, lower capacitor electrode surround the trench with a high surface concentration but low penetration depth. Such a steep doping profile is necessary in order to avoid an electrical punch-through during operation in the later trench cell.
In the 4M, in order to produce a capacitor memory cell after etching of the trench, it was previously conventional (see FIG. 5.3.2. of the aforementioned book) to use the doped monocrystalline silicon substrate directly as the first, lower capacitor electrode. The doping can, for instance, be performed by a process known from Published European Application No. 0 271 072, in which an auxiliary layer of arsenosilicate glass is first deposited, then the arsenic dopant is diffused into the silicon substrate by tempering and the auxiliary layer is finally removed again. A thin SiO.sub.2 layer is typically then applied on the highly n.sup.+ doped monocrystalline silicon electrode. The second, upper capacitor electrode is finally formed by a polysilicon electrode that simultaneously serves to fill up the trench. Since undoped polysilicon layers have very high impedance, doping is necessary. In principle, either in-situ doping during the polysilicon deposition, for example by the admixture of arsine (AsH.sub.3) with the silane (SiH.sub.4) typically used for the deposition, or the application of an additional auxiliary layer and ensuing driving-in of the dopant are necessary and possible. However, with a view toward providing an even higher scale of integration than that for the 4M, in the further course of the process the trench is already partially filled enough to result in an increase of the scale being no longer possible.
In order to make the 16-megabit DRAM, a trench-to-trench spacing of approximately 0.8 .mu.m was specified. In order for there to be no overlapping of the space charge zones at that very close spacing, the diffusion regions of the trench had to either be separated from one another by an insulating layer, or the diffusion regions had to be kept quite flat. In both cases, the monocrystalline silicon substrate can no longer directly serve to form the lower capacitor electrode. A separate electrically conductive layer must instead be deposited for that purpose. It is only then that the ONO dielectric (triple layer of silicon oxide [O] and silicon nitride [N]) and the upper polysilicon electrode can be produced as in the 4M. On one hand, the new lower electrode must have the smoothest possible surface, so that the vulnerable dielectric will undergo no loss in quality, and on the other hand the entire doping must not be above 10.sup.20 atoms per cm.sup.3, so that the ensuing process steps are not impaired, for instance by overly high growth rates of the ONO bottom oxide.
The last-mentioned requirement could be met by doping by diffusion from an arsenic glass layer, but that would necessitate several additional process steps, or in other words it would lengthen the process time. Only arsenic is possible as a doping element, because phosphorus has a relatively high diffusion coefficient and would generate overly extended diffusion regions in the trench side walls. Regarding the necessary surface quality of the new capacitor electrode, because of its particular structure, polycrystalline silicon is known to have a rough surface, while amorphous silicon, which can be deposited at a temperature below 590.degree. C., has a completely smooth surface. It is also known that at temperatures above 1000.degree. C., silicon layers deposited onto silicon wafers assume the crystal orientation of the monocrystalline silicon substrate (epitaxia).
As already mentioned, in order to avoid additional process steps, it is recommended to use in-situ doping of silicon layers, in which the quantity of silane necessary for depositing the layer is introduced into the reactor simultaneously with the dopant gas. However, undesirable interactions arise in that case, which lead to a change in the deposition rates and a non-uniform incorporation of the dopant over the length of the reactor. An article by F. C. Eversteyn et al, in the Journal of the Electrochemical Society, Vol. 120, No. 1, 1973, also teaches that particularly when arsine is used as the dopant gas, a preferential adsorption of the arsine over silane occurs at the hot wafer surface. In that kind of process, the deposition rate also decreases sharply, but a relatively high quantity of arsenic (&gt;&gt;10.sup.20 atoms per cm.sup.3) is simultaneously incorporated. That process is therefore unsuitable for producing the novel capacitor electrodes, the demand for which is discussed above.
An article by K. Sawada, in the Symposium on VLSI Technology Digest of Technical papers, Kyoto 1989, pp. 41-42, introduced a dual-stage process, in which a phosphorus-doped polysilicon layer was combined with an undoped polysilicon layer deposited immediately after it, so that the decreased deposition rate has less bearing on the results. Tempering produces a virtually homogeneously doped total layer. However, in that process as well, when arsine is used, overly highly doped silicon layers are produced, as corresponding tests have shown. Other tests showed that even if a doped amorphous silicon layer is combined with an undoped amorphous silicon layer deposited immediately thereafter, the mean total concentration of the arsenic remains above 10.sup.20 atoms per cm.sup.3, or in other words it is too high for the intended application. Although in principle it is possible to reduce the arsenic concentration by increasing the thickness of the undoped silicon layer, that would not lead to industrially desirable layer thicknesses of approximately 100 nm and below. Moreover, after the tempering, the layer surface produced by the method of K. Sawada is markedly rougher than what is typical for normal amorphous silicon deposition.